/*
* Copyright © Shanghai Awinic Technology Co., Ltd. 2020-2020. All rights reserved.
* Description: Header file in aw8680x system. Mainly for M0 related configuration register structure definition
* Date： 20201126
* Awinic_Version： aw_soc_driver_v1.0.0
*/
#include "compile_option.h"
#ifdef AW_86802

#ifndef __AW8680X_H
#define __AW8680X_H

/* Include ------------------------------------------------------------------*/
#include "aw_type.h"

#define __CM0_REV					(0)		/*!< Core Revision r0p0								 */
#define __MPU_PRESENT				(0)		/*!< STM32F0xx do not provide MPU					 */
#define __NVIC_PRIO_BITS			(2)		/*!< STM32F0xx uses 2 Bits for the Priority Levels	 */
#define __Vendor_SysTickConfig		(0)		/*!< Set to 1 if different SysTick Config is used	 */
#define __VTOR_PRESENT				(1U)	/*!< Set interrupt vector table open				 */

/*!< Interrupt Number Definition */
enum IRQn {
/****** Cortex-M0 Processor Exceptions Numbers ******************************************************/
/* undetermined */
	SysTick_IRQn   = -1,
/******  STM32F-0 specific Interrupt Numbers ********************************************************/
	IRQ_UV = 0,			/*!< Undervoltage /high voltage /ripple interruption	 */
	IRQ_TIMER0 = 1,		/*!< Timer 0 Interrupt									 */
	IRQ_TIMER1 = 2,		/*!< Timer 1 Interrupt									 */
	IRQ_UART = 3,		/*!< UART0 Interrupt									 */
	IRQ_IIC0 = 4,		/*!< IIC0 Interrupt										 */
	IRQ_AFE0 = 5,		/*!< AFE0 Interrupts									 */
	IRQ_CMP0 = 6,		/*!< AFE compare0 interruption							 */
	IRQ_CMP1 = 7,		/*!< AFE compare1 interruption							 */
	IRQ_GPIO = 8,		/*!< PA[2,4]Common interrupt							 */
	IRQ_RMC = 9,		/*!< RAM parity interrupt								 */
	IRQ_FMC = 10,		/*!< Flash controller interrupt							 */
	IRQ_WDT0 = 11,		/*!< Watchdog interruption								 */
	IRQ_SWDT = 12,		/*!< Snart Watchdog interruption						 */
	IRQ_WDT1 = 13,		/*!< Watchdog interruption								 */
};
typedef enum IRQn IRQn_Type;

#include "core_cm0plus.h"
#include <stdint.h>

/**
  * @brief SYS
  */
struct sys {
	__I  AW_U32 CHIP_ID;			/*!< Offset: 0x00      (R)   Chip id														 */
	__I  AW_U32 DATE;				/*!< Offset: 0x04      (R)   Date information												 */
	__I  AW_U32 FLS_ID;				/*!< Offset: 0x08      (R)   Flash id														 */
	__I  AW_U32 FLS_DATE;			/*!< Offset: 0x0C      (R)   Flash date information											 */
	__IO AW_U32 RESERVED0[4];		/*!< Offset: 0x10-0x1C (R/W) 																 */
	__IO AW_U32 CFG_MOD;			/*!< Offset: 0x20      (R/W) System configuration register									 */
	__IO AW_U32 RESERVED1[7];		/*!< Offset: 0x24-0x3C (R/W) 																 */
	__IO AW_U32 BIAS_EN;			/*!< Offset: 0x40      (R/W) Bias enable													 */
	__IO AW_U32 RESERVED2[15];		/*!< Offset: 0x44-0x7C (R/W) 																 */
	__IO AW_U32 PA_MFC_MUX;			/*!< Offset: 0x80      (R/W) PA pin multifunction configuration register					 */
	__IO AW_U32 PA_ADJ_DEG;			/*!< Offset: 0x84      (R/W) PA13 pin deglitch time configure								 */
	__IO AW_U32 PA_ADJ_OD;			/*!< Offset: 0x88      (R/W) PA4-PA13 pin open-drain output time configure					 */
	__IO AW_U32 PA_IN_EN;			/*!< Offset: 0x8C      (R/W) PA0-PA13 pin input enable configure							 */
	__IO AW_U32 RESERVED3;			/*!< Offset: 0x90      (R/W) 																 */
	__IO AW_U32 PA_OD_EN;			/*!< Offset: 0x94      (R/W) PA0-PA15 pin open-drain enable configure						 */
	__IO AW_U32 PA_SMIT_EN;			/*!< Offset: 0x98      (R/W) PA0-PA15 pin input interfce schmitt trigger enable configure	 */
	__IO AW_U32 PA_FAST;			/*!< Offset: 0x9C      (R/W) PA0-PA15 pin fast lane enable configure						 */
	__IO AW_U32 PA_PD_RES;			/*!< Offset: 0xA0      (R/W) PA0-PA3, PA14-PA15 pin pull-down resistor configure			 */
	__IO AW_U32 PA_SR_CTRL1;		/*!< Offset: 0xA4      (R/W) PA0-PA3, PA14-PA15 pin output delay configure					 */
	__IO AW_U32 PA_SR_CTRL2;		/*!< Offset: 0xA8      (R/W) PA0-PA3, PA14-PA15 pin output delay configure					 */
	__IO AW_U32 PA_PU_RES;			/*!< Offset: 0xAC      (R/W) PA0-PA3, PA14-PA15 pin pull-up resistor configure				 */
	__IO AW_U32 RESERVED4[212];		/*!< Offset: 0xB0-0x3FC(R/W) 																 */
	__IO AW_U32 WR_PROT_KEY;		/*!< Offset: 0x400     (R/W) system protection key  register								 */
	__I  AW_U32 SYS_WR_PROT;		/*!< Offset: 0x404     (R)   system write protection key  register							 */
};
typedef struct sys SYS_TYPE_S;

/**
  * @brief PWR
  */
struct pwr {
	__IO AW_U32 SLP_MOD;		/*!< Offset:0x000*4(R/W) Low power mode configuration register					 */
	__IO AW_U32 SLP_DLY;		/*!< Offset:0x001*4(R/W) Delay to enter low power mode configuration register	 */
	__IO AW_U32 PD_EN;			/*!< Offset:0x002*4(R/W) Power down mode enable configuration register			 */
	__IO AW_U32 SLP_EN;			/*!< Offset:0x003*4(R/W) sleep mode enable configuration register				 */
	__IO AW_U32 SLP_GO;			/*!< Offset:0x004*4(R/W) star low power mode configuration register				 */
	__I  AW_U32 RESERVED0[3];	/*!< Offset:0x014-0x01C(R)														 */
	__IO AW_U32 SWDT_EN;		/*!< Offset:0x008*4(R/W) swdt enable Register									 */
	__IO AW_U32 SWDT_LOAD_EN;	/*!< Offset:0x009*4(R/W) swdt reload counter enable Register					 */
	__IO AW_U32 SWDT_LOAD_CNT;	/*!< Offset:0x00A*4(R/W) swdt reload counter Register							 */
	__IO AW_U32 SWDT_INTR_CLR;	/*!< Offset:0x00B*4(R/W) swdt clear Register									 */
	__I  AW_U32 RESERVED1[5];	/*!< Offset:0x00B*(R/W) swdt clear Register										 */
	__IO AW_U32 LDO_CUR;		/*!< Offset:0x011*4(R/W) LDO output static current configuration register		 */
	__I  AW_U32 RESERVED2[14];	/*!< Offset:0x048-0x048(R)														 */
	__IO AW_U32 VS_ADJ;			/*!< Offset:0x020*4(R/W) Vs voltage configuration register						 */
	__I  AW_U32 RESERVED3;		/*!< Offset:0x084(R)															 */
	__IO AW_U32 VS_EN;			/*!< Offset:0x022*4(R/W) Vs voltage out enable configuration register			 */
	__I  AW_U32 RESERVED4[13];	/*!< Offset:0x08C-0x0BC(R)														 */
	__IO AW_U32 UVLO_ADJ;		/*!< Offset:0x030*4(R/W) UVLO configuration register							 */
	__IO AW_U32 UVLO_HVR;		/*!< Offset:0x031*4(R/W) UVLO High pressure reset control register				 */
	__I  AW_U32 RESERVED5;		/*!< Offset:0x0C8(R)															 */
	__IO AW_U32 UVLO_EN;		/*!< Offset:0x033*4(R/W) UVLO enable Register									 */
	__I  AW_U32 RESERVED6[12];	/*!< Offset:0x0D4-0x0FC(R)														 */
	__IO AW_U32 SRAM_EN;		/*!< Offset:0x040*4(R/W) SRAM enable register 									 */
};
typedef struct pwr PWR_TYPE_S;

/**
  * @brief RST
  */
struct rst {
	__IO AW_U32 PDR_EN;			/*!< Offset: 0x000*4(R/W)  PDR enable register			 */
	__IO AW_U32 CHIP_RSTN;		/*!< Offset: 0x001*4(R/W)  Chip reset control register	 */
	__IO AW_U32 MCU_RSTN;		/*!< Offset: 0x002*4(R/W)  MCU reset control register	 */
	__IO AW_U32 CPU_RSTN;		/*!< Offset: 0x003*4(R/W)  CPU reset control register	 */
	__I  AW_U32 RESERVED0[12];	/*!< Offset: 0x010-0x03c(R/W)							 */
	__IO AW_U32 AFE_RSTN;		/*!< Offset: 0x010*4(R/W)  AFE reset control register	 */
	__IO AW_U32 I2C0_RSTN;		/*!< Offset: 0x011*4(R/W)  IIC0 reset control register	 */
	__IO AW_U32 CRC_RSTN;		/*!< Offset: 0x012*4(R/W)  CRC reset control register	 */
	__IO AW_U32 HDIV_RSTN;		/*!< Offset: 0x013*4(R/W)  HDIV reset control register	 */
	__IO AW_U32 UART_RSTN;		/*!< Offset: 0x014*4(R/W)  UART reset control register	 */
	__IO AW_U32 TMER0_RSTN;		/*!< Offset: 0x015*4(R/W)  TIMER0 reset control register */
	__IO AW_U32 TMER1_RSTN;		/*!< Offset: 0x016*4(R/W)  TIMER1 reset control register */
	__IO AW_U32 GPIO_RSTN;		/*!< Offset: 0x017*4(R/W)  GPIO reset control register	 */
	__I  AW_U32 RESERVED1[8];	/*!< Offset: 0x060-0x07C(R/W)							 */
	__IO AW_U32 WDT_RSTN;		/*!< Offset: 0x020*4(R/W)  WDT reset control register	 */
};
typedef struct rst RST_TYPE_S;

/**
  * @brief  CLK
  */
struct clk {
	__I  AW_U32 RESERVED0[2];
	__IO AW_U32 CFG_EN;			/*!< Offset: 0x02*4(R/W)  config enable Control Register				*/
	__IO AW_U32 HOSC_EN;		/*!< Offset: 0x03*4(R/W)  hosc Enabled Register							*/
	__IO AW_U32 HOSC_MOD;		/*!< Offset: 0x04*4(R/W)  hosc configuration Register					*/
	__IO AW_U32 SYS_CLK_MUX;	/*!< Offset: 0x05*4(R/W)  System source selection register				*/
	__IO AW_U32 ADC_CLK_DDIV;	/*!< Offset: 0x06*4(R/W)  ADC clock allocation configuration register	*/
	__IO AW_U32 ISP_CLK_EN;		/*!< Offset: 0x07*4(R/W)  isp clk enable control register 				*/
	__IO AW_U32 ADC_CLK_EN;		/*!< Offset: 0x08*4(R/W)  adc clk enable control register				*/
	__IO AW_U32 WDT0_CLK_EN;	/*!< Offset: 0x09*4(R/W)  wdt0 clk enable control register				*/
	__IO AW_U32 WDT1_CLK_EN;	/*!< Offset: 0x0A*4(R/W)  wdt1 clk enable control register				*/
	__IO AW_U32 WDT2_CLK_EN;	/*!< Offset: 0x0B*4(R/W)  wdt2 clk enable control register				*/
	__I  AW_U32 RESERVED1;
	__IO AW_U32 SEL_CLK_DDIV;	/*!< Offset: 0x0D*4(R/W)  sel clk enable control register				*/
	__I  AW_U32 RESERVED2[2];
	__IO AW_U32 AFE_CLK_EN;		/*!< Offset: 0x10*4(R/W)  afe clk enable control register				*/
	__IO AW_U32 I2C0_CLK_EN;	/*!< Offset: 0x11*4(R/W)  i2c0 clk enable control register				*/
	__IO AW_U32 CRC_CLK_EN;		/*!< Offset: 0x12*4(R/W)  crc clk enable control register				*/
	__IO AW_U32 HDIV_CLK_EN;	/*!< Offset: 0x13*4(R/W)  hdiv clk enable control register				*/
	__IO AW_U32 UART_CLK_EN;	/*!< Offset: 0x14*4(R/W)  uart clk enable control register				*/
	__IO AW_U32 TMR0_CLK_EN;	/*!< Offset: 0x15*4(R/W)  timer0 clk enable control register			*/
	__IO AW_U32 TMR1_CLK_EN;	/*!< Offset: 0x16*4(R/W)  timer1 clk enable control register			*/
	__IO AW_U32 GPIO_CLK_EN;	/*!< Offset: 0x17*4(R/W)  gpio clk enable control register				*/
};
typedef struct clk CLK_TYPE_S;

/**
  * @brief FMC
  */

struct fmc {
	__IO AW_U32 ISP_CR;				/*!< Address offset: 0x00 (R/W) ISP Control Register								 */
	__IO AW_U32 ISP_ADR;			/*!< Address offset: 0x04 (R/W) ISP Flash address register							 */
	__IO AW_U32 ISP_WDAT0;			/*!< Address offset: 0x08 (R/W) ISP write data register (for write one word)		 */
	__I  AW_U32 ISP_RDAT0;			/*!< Address offset: 0x0C (R)   ISP read data register (for read one word)			 */
	__IO AW_U32 ISP_CMD;			/*!< Address offset: 0x10 (R/W) ISP instruction register							 */
	__IO AW_U32 ISP_GO;				/*!< Address offset: 0x14 (R/W) ISP trigger register								 */
	__IO AW_U32 RESERVED0[10];		/*!< Address offset: 0x18-0x3C  (R/W) 												 */
	__IO AW_U32 T_NVS;				/*!< Address offset: 0x40 (R/W) PROG/ERASE/CEb/NVR/Address to WEb Setup time 		 */
	__IO AW_U32 T_PGS;				/*!< Address offset: 0x44 (R/W) W Eb low to PROG2 high Setup time 					 */
	__IO AW_U32 T_PROG;				/*!< Address offset: 0x48 (R/W) Byte Program Time 									 */
	__IO AW_U32 T_RCV;				/*!< Address offset: 0x4C (R/W) WEb High to PROG/ERASE Low Setup time				 */
	__IO AW_U32 T_RW;				/*!< Address offset: 0x50 (R/W) Latency to next operation after PROG/ ERASE low		 */
	__IO AW_U32 T_ERASE;			/*!< Address offset: 0x54 (R/W) erase operation execution time						 */
	__IO AW_U32 T_WAKEUP;			/*!< Address offset: 0x58 (R/W) wake-up time										 */
	__IO AW_U32 RESERVED1[9];		/*!< Address offset: 0x5C-0x7C (R/W) 												 */
	__IO AW_U32 ISP_WDAT[16];		/*!< Address offset: 0x80-0xBC (R/W) ISP write data register (first word)			 */
	__I  AW_U32 ISP_RDAT[16];		/*!< Address offset: 0xC0-0xFC (R)   ISP write data register (first word)			 */
};
typedef struct fmc FMC_TYPE_S;

/**
  * @brief RMC
  */
struct rmc {
  __IO AW_U32 RMCON;			/*!< SRAM Control Register,	Address offset: 0x00 */
};
typedef struct rmc RMC_TYPE_S;

/**
  * @brief HDIV
  */
struct hdiv {
	__IO AW_U32 DIVIDEND;	/*!< Offset: 0x00 (R/W)  Divised Source Register	 */
	__IO AW_U32 DIVISOR;	/*!< Offset: 0x04 (R/W)  Divisor Source Register	 */
	__IO AW_U32 DIVQUO;		/*!< Offset: 0x08 (R/W)  Quotient result register	 */
	__IO AW_U32 DIVREM;		/*!< Offset: 0x0C (R/W)  Remainder Result Register	 */
	__IO AW_U32 DIVSTS;		/*!< Offset: 0x10 (R/W)  Divisor state register		 */
};
typedef struct hdiv HDIV_TYPE_S;

/**
  * @brief CRC
  */
struct crc {
	__IO AW_U32 DR;		/*!< Offset: 0x00 (R/W)  Data Register					  */
	__IO AW_U32 IDR;	/*!< Offset: 0x04 (R/W)  Independent Data Register		  */
	__IO AW_U32 CR;		/*!< Offset: 0x08 (R/W)  Control Register				  */
	__IO AW_U32 INIT;	/*!< Offset: 0x0C (R/W)  CRC Initial Value Register		  */
	__IO AW_U32 RSLT;	/*!< Offset: 0x10 (R/W)  CRC Calculation result register  */
	__IO AW_U32 XOR;	/*!< Offset: 0x14 (R/W)  CRC Result exclusive or register */
};
typedef struct crc CRC_TYPE_S;

/**
  * @brief WDT
  */
struct wdt {
	__IO AW_U32 CTRL;				/*!< Offset: 0x00(R/W)	Control register				*/
	__IO AW_U32 RANGE;				/*!< Offset: 0x04(R/W)	Timeout range register			*/
	__IO AW_U32 CURRENT;			/*!< Offset: 0x08(R/W)	Current counter value register	*/
	__O  AW_U32 RESTART;			/*!< Offset: 0x0c(W)	Counter restart register		*/
	__I  AW_U32 STATUS;				/*!< Offset: 0x10(R)	Interrupt status register		*/
	__I  AW_U32 ICR;				/*!< Offset: 0x14(R)	Interrupt clear register		*/
};
typedef struct wdt WDT_TYPE_S;

/**
  * @brief UART
  */
struct uart {
	__IO AW_U32 DIV_LL;				/*!< Offset: 0x00 (R/W)	Divisor Latch (Low)				*/
	__IO AW_U32 INTEN;				/*!< Offset: 0x04 (R/W)	Interrupt Enable Register		*/
	__O  AW_U32 FIFO_CTRL;			/*!< Offset: 0x08 (W)	FIFO Control Register			*/
	__IO AW_U32 LINE_CTRL;			/*!< Offset: 0x0C (R/W)	Line Control Register 			*/
	__IO AW_U32 RESERVED0;			/*!< Offset: 0x10 (R)	Line Status Register			*/
	__I  AW_U32 LINE_STATUS;		/*!< Offset: 0x14 (R)	Line Status Register			*/
	__IO AW_U32 RESERVED1[22];		/*!< Offset: 0x18-0x6C(R)								*/
	__IO AW_U32 FIFO_ACC;			/*!< Offset: 0x70 (R/W)	FIFO Access Register			*/
	__I  AW_U32 TXFIFO_RD;			/*!< Offset: 0x74 (R)	Transmit FIFO Read				*/
	__O  AW_U32 RXFIFO_WR;			/*!< Offset: 0x78 (W)	Receive FIFO Write				*/
	__I  AW_U32 UART_STATUS;		/*!< Offset: 0x7C (R)	UART Status Register			*/
	__I  AW_U32 TXFIFO_LEV;			/*!< Offset: 0x80 (R)	Transmit FIFO Level				*/
	__I  AW_U32 RXFIFO_LEV;			/*!< Offset: 0x84 (R)	Receive FIFO Level				*/
};
typedef struct uart UART_TYPE_S;

/**
  * @brief TIMER
  */
struct timer {
__IO AW_U32 LC;						/*!< Offset: 0x00 (R/W)	Value to be loaded into Timer									*/
__I  AW_U32 CV;						/*!< Offset: 0x04 (R)	Current Value of Timer											*/
__IO AW_U32 CR;						/*!< Offset: 0x08 (R/W)	Control Register for Timer										*/
__I  AW_U32 EOI;					/*!< Offset: 0x0C (R)	Returns all zeroes (0) and clears all active interrupts			*/
__I  AW_U32 STAT;					/*!< Offset: 0x10 (R)	Contains the interrupt status of all timers in the component.	*/
};
typedef struct timer TIMER_TYPE_S;

/**
  * @brief I2C0
  */
struct i2c {
	__IO AW_U32 CONTROL;			/*!< Offset: 0x00 (R/W)	I2C Control									*/
	__IO AW_U32 TAR_ADDR;			/*!< Offset: 0x04 (R/W)	I2C Target Address							*/
	__IO AW_U32 SLV_ADDR;			/*!< Offset: 0x08 (R/W)	I2C slave address							*/
	__IO AW_U32 RESERVED0;			/*!< Offset: 0x0C (R/W)												*/
	__IO AW_U32 DA_BUF_CMD;			/*!< Offset: 0x10 (R/W)	I2C Rx/Tx Data Buffer and Command			*/
	__IO AW_U32 ST_SCLH_CNT;		/*!< Offset: 0x14 (R/W)	Standard speed I2C Clock SCL High Count		*/
	__IO AW_U32 ST_SCLL_CNT;		/*!< Offset: 0x18 (R/W)	Standard speed I2C Clock SCL Low Count		*/
	__IO AW_U32 FT_SCLH_CNT;		/*!< Offset: 0x1C (R/W)	Fast speed I2C Clock SCL High Count			*/
	__IO AW_U32 FT_SCLL_CNT;		/*!< Offset: 0x20 (R/W)	Fast speed I2C Clock SCL Low Count			*/
	__IO AW_U32 RESERVED1[2];		/*!< Offset: 0x24-0x28 (R/W)										*/
	__I  AW_U32 INT_STATUS;			/*!< Offset: 0x2C (R)	I2C Interrupt Status						*/
	__IO AW_U32 INT_FLAG;			/*!< Offset: 0x30 (R/W)	I2C Interrupt Mask							*/
	__I  AW_U32 RAW_INT_STATUS;		/*!< Offset: 0x34 (R)	I2C Raw Interrupt Status					*/
	__IO AW_U32 RX_FIFO_TH;			/*!< Offset: 0x38 (R/W)	I2C Receive FIFO Threshold					*/
	__IO AW_U32 TX_FIFO_TH;			/*!< Offset: 0x3C (R/W)	I2C Transmit FIFO Threshold					*/
	__I  AW_U32 CLR_INT;			/*!< Offset: 0x40 (R)	Clear Combined and Individual Interrupts	*/
	__I  AW_U32 CLR_RX_UD_INT;		/*!< Offset: 0x44 (R)	Clear RX_UNDER Interrupt					*/
	__I  AW_U32 CLR_RX_OV_INT;		/*!< Offset: 0x48 (R)	Clear RX_OVER Interrupt						*/
	__I  AW_U32 CLR_TX_OV_INT;		/*!< Offset: 0x4C (R)	Clear TX_OVER Interrupt						*/
	__I  AW_U32 CLR_RD_REQ_INT;		/*!< Offset: 0x50 (R)	Clear RD_REQ Interrupt						*/
	__I  AW_U32 CLR_TX_ABRT_INT;	/*!< Offset: 0x54 (R)	Clear TX_ABRT Interrupt						*/
	__I  AW_U32 CLR_RX_DONE_INT;	/*!< Offset: 0x58 (R)	Clear RX_DONE Interrupt						*/
	__I  AW_U32 CLR_ACTIVITY_INT;	/*!< Offset: 0x5C (R)	Clear ACTIVITY Interrupt					*/
	__I  AW_U32 CLR_STOP_DET_INT;	/*!< Offset: 0x60 (R)	Clear STOP_DET Interrupt					*/
	__I  AW_U32 CLR_STAR_DET_INT;	/*!< Offset: 0x64 (R)	Clear START_DET Interrupt					*/
	__I  AW_U32 CLR_GEN_CAL_INT;	/*!< Offset: 0x68 (R)	Clear GEN_CALL Interrupt					*/
	__IO AW_U32 ENABLE;				/*!< Offset: 0x6C (R/W)	I2C Enable									*/
	__I  AW_U32 STATUS;				/*!< Offset: 0x70 (R)	I2C Status register							*/
	__I  AW_U32 TX_FIFO_LEVEL;		/*!< Offset: 0x74 (R)	Transmit FIFO Level Register				*/
	__I  AW_U32 RX_FIFO_LEVEL;		/*!< Offset: 0x78 (R)	Receive FIFO Level Register					*/
	__IO AW_U32 SDA_HOLD_TIME;		/*!< Offset: 0x7C (R/W)	SDA hold time length register				*/
	__IO AW_U32 TX_ABRT_STATUS;		/*!< Offset: 0x80 (R/W)	I2C Transmit Abort Status Register			*/
	__IO AW_U32 RESERVED2[4];		/*!< Offset: 0x84-0x90 (R/W)										*/
	__IO AW_U32 SDA_SETUP_TIME;		/*!< Offset: 0x94 (R/W)	I2C SDA Setup Register 						*/
	__IO AW_U32 ACK_GEN_CALL;		/*!< Offset: 0x98 (R/W)	I2C ACK General Call Register				*/
	__I  AW_U32 ENABLE_STATUS;		/*!< Offset: 0x9C (R)	I2C Enable Status Register					*/
	__IO AW_U32 FS_SPK_LIMIT;		/*!< Offset: 0xA0 (R/W)	ISS and FS spike suppression limit			*/
	__IO AW_U32 HS_SPK_LIMIT;		/*!< Offset: 0xA4 (R/W)	HS spike suppression limit					*/
};
typedef struct i2c I2C_TYPE_S;

/**
  * @brief AFE
  */
struct afe_chx {
	__IO AW_U32 ADCH_CR0;		/*!< Offset: 0x00 (R/W)  ADC Configuration Register0			*/
	__IO AW_U32 ADCH_CR1;		/*!< Offset: 0x04 (R/W)  ADC Configuration Register1			*/
	__IO AW_U32 DACH_CR;		/*!< Offset: 0x08 (R/W)  DAC control Register					*/
	__IO AW_U32 DACH_DR;		/*!< Offset: 0x0C (R/W)  DAC Data Register0						*/
	__I  AW_U32 ADCH_DR;		/*!< Offset: 0x10 (R)    ADC Data Register0						*/
	__IO AW_U32 RESERVED1[3];	/*!< Offset: 0x14-0x1C											*/
};
typedef struct afe_chx AFE_CHX_TYPE_S;

struct afe {
	__IO AFE_CHX_TYPE_S ADC_CHX[32];	/*!< Offset: 0x00-0x3FF       ADC Channel configuration				*/
	__IO AW_U32 ADMCR;					/*!< Offset: 0x400     (R/W)  ADC Mode Control Register				*/
	__IO AW_U32 ADTDR;					/*!< Offset: 0x404     (R/W)  ADC Trigger Delay Control Register	*/
	__IO AW_U32 ADSR;					/*!< Offset: 0x408     (R/W)  ADC state Register					*/
	__IO AW_U32 ADCMPCR0;				/*!< Offset: 0x40C     (R/W)  ADC Compare  Register0				*/
	__IO AW_U32 ADCMPCR1;				/*!< Offset: 0x410     (R/W)  ADC Compare  Register1				*/
	__IO AW_U32 ADCHEN;					/*!< Offset: 0x414     (R/W)  ADC enable Register					*/
	__IO AW_U32 DAOSDR;					/*!< Offset: 0x418     (R/W)  DAC offset Calibration  Register0		*/
};
typedef struct afe AFE_TYPE_S;

struct gpio_port {
	__IO AW_U32 SWPOT_DR;			/* Offset: 0x000 (R/W) Data Register			 */
	__IO AW_U32 SWPOT_DDR;			/* Offset: 0x004 (R/W) Data Direction Register	 */
	__IO AW_U32 CTRL;				/* Offset: 0x008 (R/W) Control Register			 */
};
typedef struct gpio_port GPIO_PORT_TYPE_S;

/**
  * @brief GPIOA
  */
struct gpio {
	__IO AW_U32 SWPOT_DR;			/* Offset: 0x00 (R/W)	Port A data register							*/
	__IO AW_U32 SWPOT_DDR;			/* Offset: 0x04 (R/W)	Port A data direction register					*/
	__IO AW_U32 RESERVED0[10];		/* Offset: 0x08-0x2C (R/W)												*/
	__IO AW_U32 INT_EN;				/* Offset: 0x30 (R/W)	Interrupt enable register						*/
	__IO AW_U32 INT_MASK;			/* Offset: 0x34 (R/W)	Interrupt mask register							*/
	__IO AW_U32 INT_TYPE_LVL;		/* Offset: 0x38 (R/W)	Interrupt level register						*/
	__IO AW_U32 INT_POLARITY;		/* Offset: 0x3C (R/W)	Interrupt polarity register						*/
	__I  AW_U32 INT_STATUS;			/* Offset: 0x40 (R)		Interrupt status of Port A						*/
	__I  AW_U32 RAW_INT_STAT;		/* Offset: 0x44 (R)		Raw interrupt status of Port A (premasking)		*/
	__IO AW_U32 RESERVED1;			/* Offset: 0x48 (R/W)	Raw interrupt status of Port A (premasking)		*/
	__IO AW_U32 POT_EOI;			/* Offset: 0x4c (R/W)	Port A clear interrupt register					*/
	__I  AW_U32 EXT_POT;			/* Offset: 0x50 (R)		Port A external port register					*/
	__IO AW_U32 RESERVED2[3];		/* Offset: 0x54-0x5C (R)												*/
	__IO AW_U32 LS_SYNC;			/* Offset: 0x60 (R/W)	Level-sensitive synchronization enable register	*/
	__IO AW_U32 INT_BOTH_EDGE;		/* Offset: 0x68 (R/W)	both edges register								*/
	__O  AW_U32 VER_ID_CODE;		/* Offset: 0x6C (R/W)	Component Version register						*/
};
typedef struct gpio GPIO_TYPE_S;

/**
  * @brief congig
  */
struct config {
	__IO AW_U32 FIG0;			/*!< Offset: 0x00300000 (R/W) User Configuration Area Register0 */
	__IO AW_U32 FIG1;			/*!< Offset: 0x00300004 (R/W) User Configuration Area Register1 */
};
typedef struct config CONFIG_TYPE_S;

/**
  * @brief NVIC
  */
struct nvic {
	__IO AW_U32 ISER;			/*!< Offset: 0x100 (R/W)  Interrupt Set Enable Register		 */
		 AW_U32 RESERVED0[31];
	__IO AW_U32 ICER;			/*!< Offset: 0x180 (R/W)  Interrupt Clear Enable Register	 */
		 AW_U32 RSERVED1[31];
	__IO AW_U32 ISPR;			/*!< Offset: 0x200 (R/W)  Interrupt Set Pending Register	 */
		 AW_U32 RESERVED2[31];
	__IO AW_U32 ICPR;			/*!< Offset: 0x280 (R/W)  Interrupt Clear Pending Register	 */
		 AW_U32 RESERVED3[31];
		 AW_U32 RESERVED4[64];
	__IO AW_U32 IPR0;			/*!< Offset: 0x400 (R/W) IRQ0 ~ IRQ3 Priority	Register	 */
	__IO AW_U32 IPR1;			/*!< Offset: 0x404 (R/W) IRQ4 ~ IRQ7 Priority	Register	 */
	__IO AW_U32 IPR2;			/*!< Offset: 0x408 (R/W) IRQ8~ IRQ11 Priority	Register	 */
};
typedef struct nvic NVIC_TYPE_S;

/**
  * @brief IRQ
  */
struct irq {
	__IO AW_U32 IRQ0;		/*!< Offset: 0X00 (R/W)	BOD	 Interrupt Source Recognition		 */
	__IO AW_U32 IRQ1;		/*!< Offset: 0X04 (R/W)	WDT	 Interrupt Source Recognition		 */
	__IO AW_U32 IRQ2;		/*!< Offset: 0X08 (R/W)	TMR0 Interrupt Source Recognition		 */
	__IO AW_U32 IRQ3;		/*!< Offset: 0X0C (R/W)	TMR1 Interrupt Source Recognition		 */
	__IO AW_U32 IRQ4;		/*!< Offset: 0X10 (R/W)	UART0 Interrupt Source Recognition		 */
	__IO AW_U32 IRQ5;		/*!< Offset: 0X14 (R/W)	I2C0 Interrupt Source Recognition		 */
	__IO AW_U32 IRQ6;		/*!< Offset: 0X18 (R/W)	AFE0 Interrupt Source Recognition		 */
	__IO AW_U32 IRQ7;		/*!< Offset: 0X1C (R/W)	PA	 Interrupt Source Recognition		 */
	__IO AW_U32 IRQ8;		/*!< Offset: 0X20 (R/W)	CLKC Interrupt Source Recognition		 */
	__IO AW_U32 IRQ9;		/*!< Offset: 0X24 (R/W)	EXT_INT0 Interrupt Source Recognition	 */
	__IO AW_U32 IRQ10;		/*!< Offset: 0X28 (R/W)	EXT_INT0 Interrupt Source Recognition	 */
	__IO AW_U32 IRQ11;		/*!< Offset: 0X2C (R/W)	FAULT_INT Interrupt Source Recognition	 */
};
typedef struct irq IRQ_TYPE_S;

/**
  * @brief MCU
  *NMI interrupt source selection control register
  */
struct mcu {
	__IO AW_U32 NMI;
	__IO AW_U32 MCU;
};
typedef struct mcu MCU_TYPE_S;

/**
  * @brief SYS
  */
struct syst {
	__IO AW_U32 CSR;	/*!< Offset: 0x00 (R/W) SYSTICK Control Register Control and State Registerr	 */
	__IO AW_U32 RVR;	/*!< Offset: 0x04 (R/W) SYSTICK Heavy Load Value Register						 */
	__IO AW_U32 CVR;	/*!< Offset: 0x08 (R/W) SYSTICK Current value register							 */
};
typedef struct syst SYST_TYPE_S;

/**
  * @brief SCS
  */
struct scs {
	__IO AW_U32 CPUID;			/*!< Offset: 0x00 (R/W) CPUID Register									 */
	__IO AW_U32 ICSR;			/*!< Offset: 0x04 (R/W) Interrupt Control Status Register				 */
	__IO AW_U32 RESERVED0;		/*!< Offset: 0x08 (R/W) 												 */
	__IO AW_U32 AIRCR;			/*!< Offset: 0x0C (R/W) Interrupt Application and Reuse Control Register */
	__IO AW_U32 SCR;			/*!< Offset: 0x10 (R/W) System Control Register							 */
	__IO AW_U32 RESERVED1[2];	/*!< Offset: 0x14-0x18 (R/W) 											 */
	__IO AW_U32 SHPR2;			/*!< Offset: 0x1C (R/W) System Processing Function Priority Register 2	 */
	__IO AW_U32 SHPR3;			/*!< Offset: 0x20 (R/W) System Processing Function Priority Register 3	 */

};
typedef struct scs SCS_TYPE_S;


/**@addtogroup Peripheral_memory_map
  * @{
  */
#define FLASH_BASE			((AW_U32)0x01001000) /*!< FLASH base address in the alias region		 */
#define ROM_BASE			((AW_U32)0x10000000) /*!< FLASH base address in the alias region		 */
#define RAM_BASE			((AW_U32)0x20000000) /*!< SRAM base address in the alias region			 */
#define PERIPH_BASE			((AW_U32)0x40000000) /*!< Peripheral base address in the alias region	 */
#define SCS_BA				((AW_U32)0xE000E000)

/*!< Peripheral memory map */

#define APBPERIPH_BASE		 PERIPH_BASE
#define AHBPERIPH_BASE		((AW_U32)0x50000000) // AHB base address in the alias region
#define AHB2PERIPH_BASE		(PERIPH_BASE + 0x08000000)

#define SYS_BASE			(AHBPERIPH_BASE + 0x00000000)
#define PWR_BASE			(AHBPERIPH_BASE + 0x00002000)
#define RST_BASE			(AHBPERIPH_BASE + 0x00002400)
#define CLK_BASE			(AHBPERIPH_BASE + 0x00002800)
#define INT_BASE			(AHBPERIPH_BASE + 0x00003000)
#define FMC_BASE			(AHBPERIPH_BASE + 0x0000C000)
#define RMC_BASE			(AHBPERIPH_BASE + 0x0000E000)
#define HDIV_BASE			(AHBPERIPH_BASE + 0x00014000)
#define CRC_BASE			(AHBPERIPH_BASE + 0x00024000)

#define WDT0_BASE			(APBPERIPH_BASE + 0x00000000)
#define WDT1_BASE			(APBPERIPH_BASE + 0x00001000)
#define UART_BASE			(APBPERIPH_BASE + 0x00003000)
#define TMR0_BASE			(APBPERIPH_BASE + 0x00004000)
#define TMR1_BASE			(APBPERIPH_BASE + 0x00005000)
#define I2C0_BASE			(APBPERIPH_BASE + 0x00006000)
#define AFE_BASE			(APBPERIPH_BASE + 0x00008000)
#define GPIO_BASE			(APBPERIPH_BASE + 0x00009000)

#define SysTick_BASE_AW		(SCS_BA + 0x0010UL)
#define NVIC_BASE_AW		(SCS_BA + 0x0100UL)
#define SCB_BASE_AW			(SCS_BA + 0x0D00UL)				/*!< System Control Block Base Address */

/**@addtogroup Peripheral_declaration
  * @{
  */

#define CONFIG			((CONFIG_TYPE_S *)0x00300000) // User Configuration Area Register0

#define SYS				((SYS_TYPE_S *) SYS_BASE)
#define PWR				((PWR_TYPE_S *) PWR_BASE)
#define RST				((RST_TYPE_S *) RST_BASE)
#define CLK				((CLK_TYPE_S *) CLK_BASE)
#define IRQ				((IRQ_TYPE_S *) INT_BASE)
#define MCU				((MCU_TYPE_S *) (INT_BASE + 0x80))
#define FMC				((FMC_TYPE_S *) FMC_BASE)
#define SRAM			((RMC_TYPE_S *) RMC_BASE)
#define HDIV			((HDIV_TYPE_S *) HDIV_BASE)
#define CRC				((CRC_TYPE_S *) CRC_BASE)

#define WDT0			((WDT_TYPE_S *) WDT0_BASE)
#define WDT1			((WDT_TYPE_S *) WDT1_BASE)
#define UART			((UART_TYPE_S *) UART_BASE)
#define TIMER0			((TIMER_TYPE_S *) TMR0_BASE)
#define TIMER1			((TIMER_TYPE_S *) TMR1_BASE)
#define I2C0			((I2C_TYPE_S *) I2C0_BASE)	// A1923 I2C Register configuration
#define AFE				((AFE_TYPE_S *) AFE_BASE)	// A1923 AFE Register configuration
#define GPIO			((GPIO_TYPE_S *) GPIO_BASE)

#define NVIC_AW			((NVIC_TYPE_S *) NVIC_BASE_AW)
#define SYST			((SYST_TYPE_S *) SysTick_BASE_AW)
#define SCS				((SCS_TYPE_S *) SCB_BASE_AW)

#endif
#endif
